1. Field of the Invention
The present patent relates to a page buffer of a flash memory device and a data program method using the same, and more specifically, to a page buffer of a flash memory device in which a program speed can be improved and a data program method using the same.
2. Discussion of Related Art
In a NAND flash memory device, in order to program data, one data is loaded onto a page buffer and the loaded data is transferred to a bit line wherein an erased cell will be programmed. Thus, in the case where several pages are to be programmed, one data is loaded onto the page buffer, a cell is programmed according to the loaded data and the data is then stored. Next, in order to store data in a next page, data is loaded onto the page buffer and a cell is programmed.
Examples of the page buffer having this function are disclosed in U.S. Pat. No. 5,790,458 entitled “Sense Amplifier For Nonvolatile Semiconductor Memory Device”, U.S. Pat. No. 5,761,132 “Integrated Circuit Memory Devices With Latch-Free Page Buffers Therein For Preventing Read Failures” and U.S. Pat. No. 5,712,818 entitled “Data Loading Circuit For Partial Program Of Nonvolatile Semiconductor Memory”.
The conventional page buffer will now be described.
FIG. 1 is a circuit diagram showing a conventional page buffer.
Referring to FIG. 1, a page buffer circuit 10 is connected to a pair of bit lines BLe and BLo. A NMOS transistor M1 is connected between the bit line BLe and a sense node SO. The NMOS transistor M1 is controlled by a control signal BLSHFe. A NMOS transistor M2 is connected between the bit line BLo and the sense node SO. The NMOS transistor M2 is controlled by a control signal BLSHFo. A NMOS transistor M3 is connected between the bit line BLe and a control signal line VIRPWR. A NMOS transistor M4 is connected between the bit line BLo and the control signal line VIRPWR. The NMOS transistors M3 and M4 are controlled by control signals VBLe and VBLo, respectively. The aforementioned transistors M1 to M4 constitute a bit line select and bias circuit. The bit line select and bias circuit selects one of the bit lines BLe and BLo during program and read operations, connects the selected bit line to the sense node SO and floats the non-selected bit line.
A PMOS transistor M5 is connected between the power supply voltage VCC and the sense node SO. The transistor M5 is controlled by a control signal PLOAD. The page buffer circuit 10 includes a first latch LAT1 and a second latch LAT2. The first latch LAT1 consists of inverters INV1 and INV2 forming a latch and has first and second latch nodes B and /B. The second latch LAT2 consists of inverters INV3 and INV4 constituting a latch and has first and second latch nodes A and /A. A PMOS transistor M6 that is controlled by a control signal PBRST is connected between the power supply voltage VCC and the second latch node /B of the first latch LAT1. As the power supply voltage VCC is transferred according to the control signal PBRST, the first latch LAT1 is thus reset. NMOS transistors M7 and M8 are serially connected between the second latch node /B and the ground voltage VSS. The NMOS transistors M7 and M8 are controlled by a voltage level of the sense node SO and the control signal PBLCHM, respectively. In this time, the transistors M7 and M8 and the first latch LAT1 become a first latch circuit.
A PMOS transistor M9 is connected between the power supply voltage VCC and an nWDO terminal and is turned on/off according to a logical state of the first latch node B. The nWDO terminal is electrically connected to a pass/fail check circuit (not shown). A logical level of the nWDO terminal is complementary to the first latch node B. For example, if the first latch node B has a LOW level, the nWDO node is electrically connected to the power supply voltage VCC so that it has a HIGH level. If the first latch node B has a HIGH level, the nWDO node is electrically isolated from the power supply voltage VCC so that it is floated.
Meanwhile, a NMOS transistor M10 is turned on/off according to a control signal BLSLT and is connected between the sense node SO and the first latch node B of the first latch LAT1. A NMOS transistor M11 is connected between an internal node ND1 and the first latch node B. The transistor M11 is turned on/off according to a control signal PBDO. A PMOS transistor M12 is connected between the power supply voltage VCC and a first latch node A of the second latch LAT2 and is turned on/off according to a control signal PBSET. As the power supply voltage VCC is transferred to the second latch LAT2 according to the control signal PBSET, the second latch LAT2 is reset. A NMOS transistor M13 is connected between the first latch node A and the sense node SO and is controlled by a control signal PDUMP. NMOS transistors M14 and M15 are serially connected between the first latch node A and the ground voltage VSS. The NMOS transistor M14 is controlled according to a logical state of the sense node SO. The NMOS transistor M15 is controlled by a control signal PBLCHC. In this time, the transistors M14 and M15 and the second latch LAT2 become a second latch circuit.
A NMOS transistor M16 is connected between the second latch node /A of the second latch LAT2 and the internal node ND1. A NMOS transistor M17 is connected between the first latch node A of the second latch LAT2 and the internal node ND1. The NMOS transistors M16 and M17 are controlled by data signals D1 and nD1, respectively, which have a complementary level.
If a program data bit loaded onto the page buffer circuit 10 is ‘1’, for example, the data signal D1 has a logical HIGH level and the data signal nD1 has a logical LOW level. The internal node ND1 is connected to a data line DL through the NMOS transistors M18 and M19 that constitute the column pass gate circuit. The NMOS transistors M18 and M19 are controlled by column select signals YA and YB, respectively. A NMOS transistor M20 is connected between the data line DL and the ground voltage VSS and the transistor M20 is turned on/off according to a control signal DL_DIS.
The flash memory device having the page buffer constructed above requires twice loading operations ad twice program operations in order to program two pages. The reason will be described in a more detailed manner as follows.
In the case of a prior art flash memory device, during a page program operation, data is loaded onto a main register (first latch), the transistors M10 and M1 are turned on by the control signals BLSLT and BLSHFe, data is located onto a bit line of a cell to be programmed, and the program operation is then performed by applying a bias needed for the program to the cell. Thereafter, in order to program a next page, the transistor M6 is turned on by the control signal PBRST and the main register (first latch) is thus reset. Next, new data is loaded onto the main register (first latch), the transistors M10 and M1 are turned on by the control signals BLSLT and BLSHFe, data is loaded onto a bit line of a cell to be programmed, and the program is then performed by applying a bias needed for the program to the cell.
In order to store data in two pages as such, twice loading operations and twice program operations are required. Thus, during the program operation, lots of time is consumed. Further, the program operation is not performed in 1 pulse, but must be carried out several times (usually 4 to 8 times) if failed cells occur through a program verification operation after the 1 pulse program operation. Therefore, there are problems in that lots of a program time is consumed and the operating speed of a device becomes thus low.